In semiconductor device manufacturing, there is an operation in which a vacuum process such as an etching process and the like is carried out on a substrate to be processed, for example, a semiconductor wafer (referred to as a wafer, hereinafter). In order to carry out such a process at a high throughput, a vacuum processing apparatus called a multi-chamber system and the like is used.
Among the vacuum processing apparatuses, one having a vacuum processing chamber and an atmospheric transfer chamber has been known. An example of such a vacuum processing apparatus is shown in FIG. 1. A vacuum processing apparatus 100 is composed of a load port 110 provided with a stage on which a carrier C such as a Front Opening Unified Pod (FOUP) and the like that houses plural (e.g., twenty five) wafers W is placed, a transfer module (TM) 111 that has a transfer arm for transferring the wafer W and is kept under a vacuum environment, four processing modules (PM) 112a through 112d that are arranged around the transfer module (TM) 111 and where predetermined processes are carried out on the wafer W, a loader module (LM) 114 that has a substrate transfer portion provided with a transfer arm that transfers the wafer and is kept under an aerial environment, two load lock modules (LLM) 115 that are arranged between the loader module 114 and the transfer module 111 and whose inner space is switchable between a vacuum environment and a normal pressure aerial environment, and an alignment chamber (ORT) (not shown) that is arranged adjacent to the loader module 114 and carries out pre-alignment of a position of the wafer W. Reference symbols G11 and G12 in FIG. 1 represent gate valves.
A transfer route of the wafer in the vacuum processing chamber 100 is briefly stated. The wafer W that is unprocessed and stored in the carrier C on the load port 110 is transferred to LM114, ORT, LLM115, TM111, and PMs112a through 112d in this order. Then, after an etching process, for example, is carried out under an environment of a predetermined processing gas in the processing modules 112 through 112d, the processed wafer W is transferred to TM111, LM115, LM114, and the load port 110 in this order.
When the processed wafer W is transferred back to the load port 110, there may be a problem of so-called cross-contamination in which reaction products on the processed wafer W react with moisture in the atmosphere to produce a gas and this gas may be condensed on an unprocessed wafer W, thereby causing device defects. As measures against such cross-contamination, a purge storage 113 that stores the processed wafer W in an aerial environment is provided to the loader module 114.
In addition, in the substrate processing apparatus 100, when an inside of a processing chamber of the processing modules 112a through 112d is cleaned with a cleaning gas, a dummy substrate DW may be placed on a susceptor provided in the processing chamber in order to prevent a susceptor surface of the susceptor from being etched. A dummy storage 116 that stores such a dummy substrate DW is attached to the loader module 114 in a different position from the position where the purge storage 113 is attached.
However, because the substrate processing apparatus 100 so configured requires installing spaces for the storages 113, 116 depending on kinds of the storages, and the installing spaces and the number of the wafers to be stored are restricted due to an access area of the transfer arm, flexibility in designing a layout of the apparatus is limited and a foot print may not be reduced.
Patent document 1 describes a semiconductor fabrication apparatus in which a substrate transfer portion in a transfer chamber can access a wafer cassette and a dummy storage by providing the dummy storage below a carrier susceptor arranged in a cassette chamber and elevating the carrier susceptor. However, Patent document 1 does not describe a technology for storing plural kinds of wafers in the apparatus, or address an apparatus layout problem.
Patent document 1: Japanese Patent Application Laid-Open Publication No. 2002-222844 (paragraphs 0019 through 0029, FIG. 1)